The present invention relates to techniques for grouping circuits into logic blocks, and more particularly, to techniques for grouping lookup tables, registers and other circuits into logic blocks that allow the circuits to be separated and moved independently during placement of a circuit design for a programmable integrated circuit.
A field programmable gate array (FPGA) is a programmable integrated circuit. Programmable integrated circuits also include programmable logic devices (PLDs), programmable logic arrays (PLAs), configurable logic arrays, etc. Many programmable integrated circuits are hybrids of FPGAs and ASICs (application specific integrated circuits).
Programmable integrated circuits typically include configurable logic blocks, programmable routing resources, and programmable input/output (I/O) blocks. Configurable logic blocks typically contain combinatorial components such as multiplexers and lookup tables as well as sequential components such as registers. Logic blocks implement user defined logic functions.
Lookup tables are the basic logic circuit in many of today's FPGAs. A lookup table (LUT) includes memory cells that can store the truth tables of an arbitrary function. A LUT with k inputs can implement a function with k input variables. The binary value of the input signals are used as a memory address to access one of the LUT memory locations. The LUT outputs the bits that are stored in the accessed memory location.
Lookup tables and other circuits in the FPGA are selected to implement equivalent functions performed by circuits in the user design. This selection process involves synthesis and technology mapping. During technology mapping, networks of logic gates in the user-made design are transformed into circuits such as LUTs and registers that can be placed onto the FPGA.
The user-made design is converted into a netlist. The netlist pattern organizes the LUTs and registers into logic blocks. The LUTs and registers cannot be subsequently removed from the logic blocks without violating design rules of the FPGA. The logic blocks are typically grouped into clusters of logic blocks based on routing and timing issues. The clusters of logic blocks are often called logic array blocks (LABs).
After synthesis and technology mapping, a placement tool places each of the LABs generated during synthesis to particular LABs on the FPGA. A routing tool then configures the programmable routing resources on the FPGA to connect the LABs together according to the requirements of the user design.
During placement, routability and timing issues between logic blocks become apparent that were not apparent during synthesis. For example, a synthesis tool may group a LUT and a register in the same logic block. During placement, it may become clear that routability would be improved if the LUT and the register were placed into different logic blocks on an FPGA.
However, a placement tool cannot separate the LUT and register without potentially violating design rules of the FPGA. FPGAs have design rules that limit which LUTs and registers can be placed into the same logic block and the same LAB. The design rules are constraints imposed by the particular architecture of the FPGA.
Therefore, it would be desirable to provide techniques for grouping LUTs and registers into logic blocks so that they can be more flexibly rearranged without violating design rules of the programmable integrated circuit.